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Additional info for Raytheon transistor applications : more than 50 practical circuits using Raytheon CK722 transistors : complete how-to-do-it instructions
Where possible, we report the results of the TRIPS compiler and the hand-optimized code. We have not optimized any of the SPEC programs by hand and are working to improve compiler code quality to approach that of hand-optimized. 1 Distributed Protocol Overheads To measure the contributions of the different microarchitectural protocols, we computed the critical path of the program and attributed each cycle to one of a number of categories. These categories include instruction distribution delays, operand network latency (including both hops and contention), execution overhead of instructions to fan operands out to multiple target instructions, ALU contention, time spent waiting for the global control tile (GT) to be notified that all of the block outputs (branches, registers, stores) have been produced, and the latency for the block commit protocol to complete.
The motherboard also includes a PowerPC 440GP embedded processor chip, a Xilinx FPGA chip, a flash EEPROM chip, and voltage regulators. The PowerPC chip runs an embedded Linux operating system and serves as both an OS offload processor for the TRIPS prototype chip and as a conduit between the TRIPS chips on a motherboard and a monitor running on a host computer. The monitor connects to the PowerPC via a 100 Mbit ethernet and can access all of the memory and the registers on each of the TRIPS chips for the purposes of program execution and debugging.
2 Dataflow Architectures The work most similar to TRIPS are the two recent dataflow-like architectures that support imperative programming languages such as C. These architectures, developed concurrently with TRIPS, are WaveScalar  and ASH . WaveScalar breaks programs into blocks (or “waves”) similar to TRIPS, but differs in the execution model because all control paths are mapped and executed, instead of the one speculated control path of TRIPS. Other major differences include dynamic, rather than static placement of instructions, no load speculation, and more hierarchy in the networks, because WaveScalar provides many more execution units than TRIPS.
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